詹姆士·波默林——IAS和HARVEST计算机的首席工程师
1986年计算机先驱奖获得者之一的詹姆士·波默林(James H．Pomerene)（1920 - 2008）是冯·诺伊曼在普林斯顿高级研究所研制IAS计算机项目中的首席工程师，后来又在IBM公司主持设计了HARVEST计算机。由于他“对IAS和HARVEST计算机”(For IAS and Harvest Computers)所作出的贡献，IEEE授予他计算机先驱奖。
James H．Pomerene波默林1920年6月22日生于美国纽约州东南端的扬克斯(Yonkers，N．Y．)，离纽约市不远。1942年在西北大学取得电气工程学士学位以后，进入Hazeltine公司工作，曾参与敌我识别雷达(IFF，Identification Of Friend Or Foe或Interrogator Friend Or Foe)的研制，负责微波与脉冲调制器方面的工作。战后，1946年4月，他接受冯·诺伊曼和哥尔斯廷的邀请，到普林斯顿大学参与IAS计算机的研制。IAS计算机决定采用威廉姆斯管作存储器，但威廉姆斯管能否长期保存信息却是一个令大家都十分担心的问题。波默林挺身而出，承担起了解决这一难题的任务。经过反复试验，波默林终于取得成功，使威廉姆斯管能长期地保存16个二进制位。这使IAS方案中的一个关键获得落实，即用40个CRT组成lAS中的并行存储器，每个CRT存储一个计算机字的一位。IAS存储器系统的开发与建造完全由波默林负责。到1951年8月，波默林由于他在项目中的出色表现而被任命为lAS计划的首席工程师(chief engineer)。他担任这个职务直至1956年项目组解散。
IAS计算机于1951年1月基本完成，经过洛斯阿拉莫斯实验室用设计氢弹的程序考核(这个程序IAS计算机连续运行了60天才完成)，1952年6月正式向公众展示。以后经过不断改进、完善，于1960年退役。它本身虽作为样机只制造了一台，但在研制过程中，美国的许多研究机构和大学就对IAS进行仿制，比如我们已经提到过，阿尔贡国立实验室的AVIDAC、ORACLE，伊利诺大学的ORDVAC、ILLIAC，洛斯阿拉莫斯国立实验室的MANIAC，等等，就都是以IAS为原型的。所以，IAS在计算机发展史上占有重要地位。
James H. Pomerene（右）普林斯顿大学的IAS研制组解散以后，波默林加盟IBM公司，参与了IBM公司第一台流水线计算机STRETCH的研制。后来，美国国家安全局NSA(National Security Agency)要求IBM公司为他们生产一台功能更强的计算机，波默林受命和其他一些人(包括另一位计算机先驱奖获得者布鲁克斯)制定方案和进行设计，这就是后来的HARVEST。波默林在HARVEST的方案和设计中，巧妙地以已经获得成功的STRETCH为基础，加上一个“字节向量流水线部件”(byte vector pipeline unit)用以处理大量的非数值数据。这个方法既使HARVEST的研制大大缩短了周期，同时又使HARVEST的处理能力获得很大提高，满足了国家安全局的需要。此外，HARVEST还具有以下两个不寻常的特点：第一，它具有两级程序控制，第一级用来建立进程，包括为了从内存进行读写而对字节进行匹配；第二级再对由第一级建立的进程进行操作。第二，它的磁带机和磁带子程序库系统很先进，不但容量很大，而且是完全自动的。
HARVEST于1962年完成以后，波默林开始研究多处理机系统，其结果是推出了IBM公司的第一个商用多处理机系统，即IBMMod65MP。1965年，波默林领导一个小组开始设计并行网络数字计算机PNDC(Parallel Network Digital Computer)，这是最早的单指令流、多数据流即SIMD机的原型。PNDC虽然只停留在设计阶段，没有实际建造，但它的一些思想，如包含高速缓冲存储器在内的多级存储器系统等，在以后的系统中获得了发展和使用。
个人简介回目录
James H. Pomerene was born in Yonkers, New York on 22 June 1920. After receiving the B.S. degree in Electrical Engineering from Northwestern University in June, 1942, he joined the Hazeltine Corporation and was involved with the design of IFF (Identification Friend or Foe) radar working in both the microwave and pulse modulator areas.
In April, 1946, Pomerene accepted an invitation from John von Neumann and Herman Goldstine to join the newly organized Electronic Computer Project at the Institute for Advanced Study in Princeton, New Jersey. This project built a parallel stored program computer that was the prototype for a number of machines such as the Maniac, Oracle, Illiac, etc. Pomerene designed the adder portion of the arithmetic unit and then was entirely responsible for the development and construction of the electrostatic (Williams Tube) memory. In August, 1951, he was appointed Chief Engineer of the project, a position he held until the project was disbanded in 1956.
Pomerene then joined the IBM Corporation in Poughkeepsie, New York where he and several others conducted a study which began the development of the Harvest computer. Harvest consisted of a Stretch computer for standard processing plus a byte vector pipeline unit for processing non-numeric data. Harvest had two levels of program control: one level set up a process, including the pattern for fetching and storing bytes from and to memory, and the second le-.,el operated on that process. It also had a remarkable tape and tape library system, fully automatic and of great capacity.
Following the completion of Harvest, Pomerene studied the use of multiple processors as a way to increase both compute capacity and system availability. In 1965, he headed a team doing the preliminary design of the Parallel Network Digital Computer (PNDC), an early parallel machine. The PNDC was not built, but work on it led Pomerene to the idea of making a highly available memory system out of a number of memory units, each storing one bit position of a word.
Pomerene began a special study of a highly available system based on this memory. As envisioned, the memory would read out a block of words and it was conjectured that this block readout could be useful if each processor in the system were provided with a local memory holding a number of recently used blocks. This arrangement, now known as a cache, was simulated and the results were much better than expected. Subsequently the cache was incorporated in the Model 85 processor. In 1967 Pomerene was promoted to the position of Senior Staff Member at corporate headquarters in Armonk, New York. He was appointed an IBM Fellow in 1976 and soon transferred to the Research Division.
Pomerene was a Life Fellow of the IEEE and a member of the National Academy of Engineering. He authored or co-authored numerous technical papers and one book, and held singly and jointly seventeen patents. Pomerene received the IBM Outstanding Innovation Award in 1968, the IEEE Computer Society's Pioneer Award in 1986, and the IEEE Edison Medal in 1993 "For outstanding contributions to the development of computer architecture, including pipelining, reliable main memory and memory hierarchies". He was married to Edythe R. Pomerene; they had three children, James B., Katherine E., and Andrew T. S. He died 7 December 2008 in Chappaqua, New York.
